The present invention relates to semiconductor integrated circuits, e.g., a technique advantageous for dynamic RAMs (random access memories) which are directed to higher speed and lower power consumption.
Japanese unexamined patent publication No. 8-181292 discloses an example of dynamic RAMs which have a hierarchical word line configuration and a triple well structure including an N-well of a great depth.
In a dynamic RAM, a plurality of internal voltages are developed from a power supply voltage supplied through an external terminal and are supplied to internal circuit blocks. For example, a method of operating internal circuits using a voltage (3V) as a result of a voltage drop from an external power supply voltage VDD (5V) has been widely used since the advent of 16 Mbit dynamic RAMs in order to maintain the reliability of fine devices and to reduce power consumption. The 64 Mbit generation is directed to lower operating voltages in internal circuits, e.g., an external voltage VDD drops to 3.3 V to supply a low voltage on the order of 2.5 v to capacitors of memory cells, and, further, peripheral circuits are also operated at the dropped voltage.
A dynamic memory cell must be formed to have a high threshold voltage in order to prevent a reduction of information retention time attributable to a leakage current in an off state and a leakage current caused by the lifting of a word line. It is desirable to reduce the operating voltage of internal circuits over than the memory cells to reduce power consumption, and the threshold voltage of MOSFETs (hereinafter, imply MOSFETs according to general recognition) is preferably low in order to maintain a desired operating speed at such a low voltage.
In conventional dynamic RAMs, in order to satisfy the conflicting requirements described above, a MOSFET having a relatively high threshold voltage is formed in consideration of the information retention time at the memory cell and the operating speed of peripheral circuits as described above. The three-well structure described above electrically isolates P-type well regions where MOSFETs of memory cells are formed and P-type well regions or a substrate where MOSFETs of peripheral circuits are formed; a negative backward bias voltage is supplied to channel regions of MOSFETs that form address selection MOSFETs of memory cells to make a correction to increase a threshold voltage thereof; the ground potential of the circuit is supplied to channel regions of MOSFETs forming the peripheral circuits; and the impurity concentration of the channel regions is corrected to a lower value to make an adjustment to reduce the threshold voltage using an ion implantation technique.
The inventors have studied the possibility of a reduction in the operating voltage of a dynamic RAM provided with a mass storage capacity, e.g., 256 Mbits to 2 V or less in order to achieve a ether reduction in power consumption. For an operating voltage as low as 2 V or 1.8 V, the above-described technique for correcting a threshold voltage results in a problem not only in that a desired operating speed can not be achieved, but also in that process-related variations are significant. Under such circumstances, the inventors have conceived a configuration of a single semiconductor integrated circuit device utilizing MOSFETs having two kinds of gate insulation films that depend on operating voltages. The use of such MOSFETs having two kinds of gate insulation films has resulted in a new problem in that control of operations or adjustment of timing between circuits utilizing the MOSFETs having two kinds of gate insulation films requires the timing to be set based on the assumed worst case of operation timing attributable to variations in the thickness of the gate insulation films, which significantly affects the operating speed.
It is an object of the present invention to provide a semiconductor integrated circuit device in which devices can be made finer and faster with less power consumption without reducing reliability. It is another object of the present invention to provide a semiconductor integrated circuit device including dynamic RAMs in which devices are made finer and faster, and in which there is an improvement in the degree of the integration with less power consumption and without reducing reliability. The above-described and other objects and novel features of the present invention will become apparent from the description in the present specification and from the accompanying drawings.
A typical aspect of the invention disclosed in this specification can be briefly described as follows. In a semiconductor integrated circuit device in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal develops either or both of a dropped voltage and boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage developed at the internal voltage generation circuit is formed by a first MOSFET having a gate insulation film with a large thickness corresponding to the power supply voltage or the boosted voltage and a second internal circuit operating on the low voltage is formed by a second MOSFET having a gate insulation film having a small thickness corresponding to the low voltage.
Another typical aspect of the invention disclosed in the present specification can be briefly described as follows. When the second internal circuit is operated in association with the operation of the first internal circuit, an operation timing signal of the second internal circuit is formed by monitoring the state of operation of the first internal circuit by a delay circuit utilizing the first MOSFET forming a part of the first internal circuit.